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Ticket Summary Status Owner Type Priority Milestone
#4 ATMEGA8A: TWI simulation new dsl task major MCUSim-0.2
#6 ATMEGA8A: SPI simulation new dsl task major MCUSim-1.0
#8 Let LPM/ELPM instruction read fuse and lock bits new dsl task major MCUSim-0.2
#9 Update decoder to simulate multi-cycle instructions accepted dsl task major MCUSim-0.2
#12 ATMEGA328/328P: 8-bit Timer/Counter0 simulation assigned Pawel task major Work in Progress
#13 ATMEGA328/328P: 16-bit Timer/Counter1 simulation new dsl task major MCUSim-0.2
#14 ATMEGA328/328P: 8-bit Timer/Counter2 simulation assigned Pawel task major MCUSim-0.2
#18 ATMEGA8A: Configure by setting fuse bytes and lock bits assigned Alexandr task major MCUSim-0.2
#21 ATMEGA8A: External (asynchronous) clock source of the 8-bit Timer/Counter2 assigned dsl task major MCUSim-1.0
#23 Submit an MCUSim-devel FreeBSD port new dsl enhancement major MCUSim-0.2
#24 Breakpoint cannot be removed in Code::Blocks IDE new dsl defect major Patches Welcome
#26 ATMEGA8A: External clock source of the 16-bit Timer/Counter1 new dsl task major MCUSim-1.0
#27 ATMEGA8A: Set a correct reset flag in MCUCSR new dsl enhancement major MCUSim-0.2
#31 ATMEGA328/328P: Perform a hardware test to read signature bytes assigned Dmitry Salychev task major Patches Welcome
#32 ATMEGA8A: Incorrect use of the 'missed_cm' variable. assigned dsl defect major MCUSim-0.2
#33 ATMEGA328/328P: USART simulation (with pty connection) new dsl task major MCUSim-0.2
#34 Update LAC, LAS, LAT and LDS instructions to access data memory above 64 KiB new dsl enhancement major Patches Welcome
#35 ATMEGA328/328P: Simulate start-up times for the different clock sources new dsl enhancement major Patches Welcome
#39 Prepare msim_m8a code model accepted dsl task major Work in Progress
#30 ATMEGA328/328P: Toggle PORTx pins assigned Pawel task minor MCUSim-0.2
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