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Ticket Summary Status Keywords Owner Type Priority
#4 ATMEGA8A: TWI simulation new planned-in-0.2 dsl task major
#8 Let LPM/ELPM instruction read fuse and lock bits new planned-in-0.2.0 dsl task major
#9 Update decoder to simulate multi-cycle instructions accepted planned-in-0.2.0 dsl task major
#12 ATMEGA328/328P: 8-bit Timer/Counter0 simulation accepted planned-in-0.2 dsl task major
#13 ATMEGA328/328P: 16-bit Timer/Counter1 simulation accepted planned-in-0.2.0 dsl task major
#14 ATMEGA328/328P: 8-bit Timer/Counter2 simulation accepted planned-in-0.2.0 dsl task major
#18 ATMEGA8A: Configure by setting fuse bytes and lock bits assigned planned-in-0.2.0 Alexandr task major
#23 Submit an MCUSim-devel FreeBSD port accepted planned-in-0.2.0 dsl enhancement major
#24 Breakpoint cannot be removed in Code::Blocks IDE new planned-in-0.2.0 dsl defect major
#27 ATMEGA8A: Set a correct reset flag in MCUCSR new planned-in-0.2 dsl enhancement major
#31 ATMEGA328/328P: Perform a hardware test to read signature bytes assigned planned-in-0.2 dsl task major
#32 ATMEGA8A: Incorrect use of the 'missed_cm' variable. assigned planned-in-0.2 dsl defect major
#33 ATMEGA328/328P: USART simulation (with pty connection) new planned-in-0.2 dsl task major
#30 ATMEGA328/328P: Toggle PORTx pins accepted planned-in-0.2 dsl task minor
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