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Ticket Summary Status Owner Type Milestone Component
#13 ATMEGA328/328P: 16-bit Timer/Counter1 simulation accepted dsl task Work in Progress avr
#12 ATMEGA328/328P: 8-bit Timer/Counter0 simulation accepted dsl task Work in Progress avr
#14 ATMEGA328/328P: 8-bit Timer/Counter2 simulation accepted dsl task Work in Progress avr
#31 ATMEGA328/328P: Perform a hardware test to read signature bytes assigned dsl task Patches Welcome avr
#35 ATMEGA328/328P: Simulate start-up times for the different clock sources new dsl enhancement Patches Welcome avr
#33 ATMEGA328/328P: USART simulation (with pty connection) new dsl task MCUSim-0.2 avr
#18 ATMEGA8A: Configure by setting fuse bytes and lock bits assigned Alexandr task MCUSim-0.2 avr
#21 ATMEGA8A: External (asynchronous) clock source of the 8-bit Timer/Counter2 assigned dsl task MCUSim-1.0 avr
#26 ATMEGA8A: External clock source of the 16-bit Timer/Counter1 new dsl task MCUSim-1.0 avr
#32 ATMEGA8A: Incorrect use of the 'missed_cm' variable. assigned dsl defect MCUSim-0.2 avr
#6 ATMEGA8A: SPI simulation new dsl task MCUSim-1.0 avr
#27 ATMEGA8A: Set a correct reset flag in MCUCSR new dsl enhancement MCUSim-0.2 avr
#4 ATMEGA8A: TWI simulation new dsl task MCUSim-0.2 avr
#24 Breakpoint cannot be removed in Code::Blocks IDE new dsl defect Patches Welcome avr
#8 Let LPM/ELPM instruction read fuse and lock bits new dsl task MCUSim-0.2 avr
#23 Submit an MCUSim-devel FreeBSD port accepted dsl enhancement Patches Welcome avr
#34 Update LAC, LAS, LAT and LDS instructions to access data memory above 64 KiB new dsl enhancement Patches Welcome avr
#9 Update decoder to simulate multi-cycle instructions accepted dsl task MCUSim-0.2 avr
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