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Ticket Summary Owner Type Priority Milestone Component
#37 Incorrect calculation of two’s complement overflow flag in SBIW dsl defect critical MCUSim-0.2 avr
#1 ATMEGA8A: 8-bit Timer/Counter0 simulation dsl task major MCUSim-0.2 avr
#2 ATMEGA8A: 16-bit Timer/Counter1 simulation dsl task major MCUSim-0.2 avr
#3 ATMEGA8A: 8-bit Timer/Counter2 simulation dsl task major MCUSim-0.2 avr
#7 ATMEGA8A: Boot Loader Support dsl task major MCUSim-0.2 avr
#10 ATMEGA8A: USART simulation (with pty connection) dsl task major MCUSim-0.2 avr
#15 Ability to create simulated boards for tests dsl enhancement major MCUSim-0.2 mcusim-tests
#19 ATMEGA328/328P: Configure by setting fuse bytes and lock bits Pawel task major MCUSim-0.2 avr
#20 Check MISRA C:2012 rules dsl enhancement major MCUSim-0.2 avr
#28 Initialization of the AVR I/O registers dsl defect major MCUSim-0.2 avr
#29 ATMEGA328P: Incorrect TIFR register of Timer/Counter0 Pawel defect major MCUSim-0.2 avr
#36 Configuration file dsl task major MCUSim-0.2 avr
#38 Preserve a content of flash memory dsl task major MCUSim-0.2 avr
#22 Print 16-bit registers to VCD file dsl enhancement minor MCUSim-0.2 avr
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