Opened 2 years ago

Last modified 14 months ago

#12 accepted task

ATMEGA328/328P: 8-bit Timer/Counter0 simulation

Reported by: dsl Owned by: dsl
Priority: major Milestone: Work in Progress
Component: avr Keywords: planned-in-0.2


  • Internal and external clock sources
  • Normal mode
  • Clear Timer on Compare Match (CTC) mode
  • Fast PWM mode
  • Phase Correct PWM mode
  • Generate interrupts: TIMER0 OVF, TIMER0 COMPA, TIMER0 COMPB

Change History (8)

comment:1 Changed 2 years ago by dsl

Owner: changed from dsl to Pawel
Status: newassigned

comment:2 Changed 2 years ago by Pawel

Milestone: 0.2.0Work in Progress

comment:3 Changed 2 years ago by Pawel

You can follow progress on this branch:

comment:5 Changed 21 months ago by dsl

Keywords: planned-in-0.2 added; planned-in-0.2.0 removed

comment:6 Changed 18 months ago by dsl

Pawel, there is a problem with timer/counter0 I mentioned earlier.

Take a look at the timer counting mechanism:

It looks OK, but it shouldn't exist there exactly because we already have
such counting mechanisms implemented in the functions to back the different
timer's modes.

Normal mode, for example:

This is why we pass a pointer to the tc0_ticks in order to modify it within
a function and be ready to update a timer:

comment:7 Changed 14 months ago by dsl

Owner: changed from Pawel to dsl

comment:8 Changed 14 months ago by dsl

Status: assignedaccepted
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