Opened 16 months ago

Last modified 2 months ago

#13 accepted task

ATMEGA328/328P: 16-bit Timer/Counter1 simulation

Reported by: dsl Owned by: dsl
Priority: major Milestone: Work in Progress
Component: avr Keywords: planned-in-0.2.0
Cc:

Description

  • Internal and external clock source
  • Prescaling
  • Normal mode
  • Clear Timer on Compare Match (CTC) mode
  • Fast PWM mode
  • Phase Correct PWM mode
  • Phase and Frequency Correct PWM mode
  • Generate interrupts: TIMER1 CAPT, TIMER1 COMPA, TIMER1 COMPB, TIMER1 OVF

Change History (7)

comment:1 Changed 16 months ago by dsl

Implementation could be similar to #2

comment:2 Changed 9 months ago by dsl

Milestone: 0.2.00.2

Milestone renamed

comment:3 Changed 9 months ago by dsl

Milestone: 0.2MCUSim-0.2

Milestone renamed

comment:4 Changed 7 months ago by dsl

Milestone: MCUSim-0.2MCUSim 0.2

Milestone renamed

comment:5 Changed 7 months ago by dsl

Milestone: MCUSim 0.2mcusim 0.2

Milestone renamed

comment:6 Changed 5 months ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

comment:7 Changed 2 months ago by dsl

Milestone: MCUSim-0.2Work in Progress
Status: newaccepted
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