Opened 18 months ago

Last modified 4 months ago

#14 accepted task

ATMEGA328/328P: 8-bit Timer/Counter2 simulation

Reported by: dsl Owned by: dsl
Priority: major Milestone: Work in Progress
Component: avr Keywords: planned-in-0.2.0
Cc:

Description

  • Internal (synchronous) clock source
  • External (asynchronous) clock source (32.768 kHz match crystal)
  • Normal mode
  • Clear Timer on Compare Match (CTC) mode
  • Fast PWM mode
  • Phase Correct PWM mode
  • Prescaling
  • Generate interrupts: TIMER2 OVF, TIMER2 COMPB, TIMER2 COMPA

Change History (9)

comment:1 Changed 18 months ago by dsl

Implementation could be similar to #3.

comment:2 Changed 16 months ago by dsl

Owner: changed from dsl to Pawel
Status: newassigned

comment:3 Changed 11 months ago by dsl

Milestone: 0.2.00.2

Milestone renamed

comment:4 Changed 11 months ago by dsl

Milestone: 0.2MCUSim-0.2

Milestone renamed

comment:5 Changed 9 months ago by dsl

Milestone: MCUSim-0.2MCUSim 0.2

Milestone renamed

comment:6 Changed 9 months ago by dsl

Milestone: MCUSim 0.2mcusim 0.2

Milestone renamed

comment:7 Changed 7 months ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

comment:8 Changed 4 months ago by dsl

Milestone: MCUSim-0.2Work in Progress
Owner: changed from Pawel to dsl

comment:9 Changed 4 months ago by dsl

Status: assignedaccepted
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