Opened 12 months ago

Closed 5 months ago

Last modified 6 weeks ago

#2 closed task (fixed)

ATMEGA8A: 16-bit Timer/Counter1 simulation

Reported by: dsl Owned by: dsl
Priority: major Milestone: MCUSim-0.2
Component: avr Keywords: planned-in-0.2.0
Cc:

Description (last modified by dsl)

  • Internal and external clock source
  • Prescaling
  • Normal mode
  • Clear Timer on Compare Match (CTC) mode
  • Fast PWM mode
  • Phase Correct PWM mode
  • Phase and Frequency Correct PWM mode
  • Generate interrupts: TIMER1 CAPT, TIMER1 COMPA, TIMER1 COMPB, TIMER1 OVF

Change History (19)

comment:1 Changed 11 months ago by dsl

Milestone: 0.2.0Work in Progress
Status: newaccepted

comment:2 Changed 9 months ago by dsl

Description: modified (diff)

comment:3 Changed 8 months ago by dsl

Description: modified (diff)

comment:5 Changed 7 months ago by dsl

Description: modified (diff)

comment:6 Changed 7 months ago by dsl

Description: modified (diff)

comment:10 Changed 5 months ago by dsl

Description: modified (diff)

comment:11 Changed 5 months ago by dsl

comment:12 Changed 5 months ago by dsl

Description: modified (diff)

comment:13 Changed 5 months ago by dsl

Description: modified (diff)

It'll be closed in favor of https://trac.mcusim.org/ticket/26.

comment:14 Changed 5 months ago by dsl

Resolution: fixed
Status: acceptedclosed

comment:15 Changed 5 months ago by dsl

Milestone: Work in Progress0.2

comment:16 Changed 5 months ago by dsl

Milestone: 0.2MCUSim-0.2

Milestone renamed

comment:17 Changed 3 months ago by dsl

Milestone: MCUSim-0.2MCUSim 0.2

Milestone renamed

comment:18 Changed 3 months ago by dsl

Milestone: MCUSim 0.2mcusim 0.2

Milestone renamed

comment:19 Changed 6 weeks ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

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