Opened 2 years ago

Closed 2 years ago

Last modified 18 months ago

#3 closed task (fixed)

ATMEGA8A: 8-bit Timer/Counter2 simulation

Reported by: dsl Owned by: dsl
Priority: major Milestone: MCUSim-0.2
Component: avr Keywords: planned-in-0.2.0
Cc:

Description (last modified by dsl)

  • Internal (synchronous) clock source
  • External (asynchronous) clock source (32.768 kHz match crystal) (continue in #21)
  • Normal mode
  • Clear Timer on Compare Match (CTC) mode
  • Fast PWM mode
  • Phase Correct PWM mode
  • Prescaling
  • Generate interrupts: TIMER2 OVF, TIMER2 COMP

Attachments (3)

ATMEGA8A-tc2-OCR2-update-without-double-buffering.png (74.9 KB) - added by dsl 2 years ago.
Update of the OCR2 Compare Register without double buffering
ATMEGA8A-tc2-fastpwm-glitch.png (76.8 KB) - added by dsl 2 years ago.
Fast PWM glitch because of non-implemented OCR2 double buffering
ATMEGA8A-pcpwm-weird-glitch.png (63.1 KB) - added by dsl 2 years ago.
Weird glitch near the TOP border in Phase Correct PWM mode

Download all attachments as: .zip

Change History (20)

comment:1 Changed 2 years ago by dsl

Milestone: 0.2.0Work in Progress

comment:2 Changed 2 years ago by dsl

Status: newaccepted

comment:3 Changed 2 years ago by dsl

CTC mode for Timer/Counter2 has been introduced in 0.1.59: https://github.com/dsalychev/mcusim/commit/7191407b4e17d056ee07b861f63fa15b009c8c5d

comment:4 Changed 2 years ago by dsl

Description: modified (diff)

comment:5 Changed 2 years ago by dsl

There is a special case in fast PWM mode with COM21:0 = 1. It allows a frequency (with 50% duty cycle) waveform to be generated with maximum Foc2 = Fclk_io/2. It's described in details in a datasheet 22.7.3 Fast PWM Mode, but I haven't understood it completely yet. That's why I'm not going to implement it in the following patch which will bring fast PWM mode.

comment:6 Changed 2 years ago by dsl

Fast PWM mode added in 0.1.60.

However, double buffering mechanism of OCR2 Compare Register wasn't implemented. It causes weird glitches of the generated PWM (on the screenshots attached).

Last edited 2 years ago by dsl (previous) (diff)

Changed 2 years ago by dsl

Update of the OCR2 Compare Register without double buffering

Changed 2 years ago by dsl

Fast PWM glitch because of non-implemented OCR2 double buffering

comment:7 Changed 2 years ago by dsl

Double buffering of OCR2 implemented in 0.1.62.

Last edited 2 years ago by dsl (previous) (diff)

Changed 2 years ago by dsl

Weird glitch near the TOP border in Phase Correct PWM mode

comment:8 Changed 2 years ago by dsl

Description: modified (diff)

Phase Correct PWM mode added in 0.1.63 and 0.1.64.

Last edited 2 years ago by dsl (previous) (diff)

comment:9 Changed 2 years ago by dsl

Fast PWM toggle mode added in 0.1.65.

comment:10 Changed 2 years ago by dsl

Description: modified (diff)

comment:11 Changed 2 years ago by dsl

Description: modified (diff)

comment:12 Changed 2 years ago by dsl

Milestone: Work in Progress0.2.0
Resolution: fixed
Status: acceptedclosed

comment:13 Changed 22 months ago by dsl

Milestone: 0.2.00.2

Milestone renamed

comment:14 Changed 22 months ago by dsl

Milestone: 0.2MCUSim-0.2

Milestone renamed

comment:15 Changed 20 months ago by dsl

Milestone: MCUSim-0.2MCUSim 0.2

Milestone renamed

comment:16 Changed 20 months ago by dsl

Milestone: MCUSim 0.2mcusim 0.2

Milestone renamed

comment:17 Changed 18 months ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

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