Opened 17 months ago

Closed 17 months ago

Last modified 16 months ago

#37 closed defect (fixed)

Incorrect calculation of two’s complement overflow flag in SBIW

Reported by: dsl Owned by: dsl
Priority: critical Milestone: MCUSim-0.2
Component: avr Keywords: planned-in-0.2


AVR decoder doesn't handle SBIW instruction correctly by setting a two's
complement overflow flag as (R15 & (~Rdh7)). I used an AVR Instruction Set
Manual (rev. 0856L - 11/2016) blindly.

The problem can be reproduced in mcusim <= 0.1.0134.

The correct implementation of the SBIW should be:

Rdh:Rdl ← Rdh:Rdl - K, and
two's complement flag V = (Rdh7 & (~R15)),
where Rdh is a MSB of the register pair,
R is a result of subtraction

Attached archive contains a test which fails on mcusim <= 0.1.0134,
but works correctly starting from mcusim 0.1.0135.

Attachments (1)

ATMEGA8A-tc2-ctc-mode.tar.gz (6.2 KB) - added by dsl 17 months ago.

Download all attachments as: .zip

Change History (5)

Changed 17 months ago by dsl

comment:2 Changed 17 months ago by dsl

Resolution: fixed
Status: assignedclosed

comment:3 Changed 17 months ago by dsl

Milestone: Work in Progressmcusim 0.2

comment:4 Changed 16 months ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

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