Opened 20 months ago

Last modified 9 months ago

#9 accepted task

Update decoder to simulate multi-cycle instructions

Reported by: dsl Owned by: dsl
Priority: major Milestone: MCUSim-0.2
Component: avr Keywords: planned-in-0.2.0
Cc:

Description


Attachments (7)

Change History (18)

comment:1 Changed 20 months ago by dsl

I've done a piece of work here already. The only multi-cycle instructions which should be supported are LD, ST and SPM.

Last edited 18 months ago by dsl (previous) (diff)

comment:2 Changed 20 months ago by dsl

Milestone: 0.2.0Work in Progress

comment:3 Changed 19 months ago by dsl

Status: newaccepted

comment:4 Changed 18 months ago by dsl

required number of cycles per LD and ST instructions added in 0.1.73.

Changed 18 months ago by dsl

Attachment: schematic.png added

Changed 18 months ago by dsl

Changed 18 months ago by dsl

comment:5 Changed 17 months ago by dsl

It is said that number of clock cycles per SPM instruction depends on the operation. There are five operations according to the 116. SPM – Store Program Memory:

(i) (RAMPZ:Z) ← $ffff Erase Program memory page
(ii) (RAMPZ:Z) ← R1:R0 Write Program memory word
(iii) (RAMPZ:Z) ← R1:R0 Write temporary page buffer
(iv) (RAMPZ:Z) ← TEMP Write temporary page buffer to Program memory
(v) BLBITS ← R1:R0 Set Boot Loader lock bits

and six operations according to the 117. SPM #2 – Store Program Memory:

(i) (RAMPZ:Z) ← $ffff Erase Program memory page
(ii) (RAMPZ:Z) ← R1:R0 Load Page Buffer
(iii) (RAMPZ:Z) ← BUFFER Write Page Buffer to Program memory
(iv) (RAMPZ:Z) ← $fff, Z ← Z + 2 Erase Program memory page, Z post incremented
(v) BLBITS ← R1:R0, Z ← Z + 2 Load Page Buffer, Z post incremented
(vi) (RAMPZ:Z) ←BUFFER, Z ← Z + 2 Write Page Buffer to Program memory, Z post incremented

But what number of cycles should be expected per operation?!

comment:6 Changed 13 months ago by dsl

Milestone: Work in Progress0.2

comment:7 Changed 13 months ago by dsl

Milestone: 0.2Work in Progress

comment:8 Changed 13 months ago by dsl

Milestone: Work in ProgressMCUSim-0.2

comment:9 Changed 11 months ago by dsl

Milestone: MCUSim-0.2MCUSim 0.2

Milestone renamed

comment:10 Changed 11 months ago by dsl

Milestone: MCUSim 0.2mcusim 0.2

Milestone renamed

comment:11 Changed 9 months ago by dsl

Milestone: mcusim 0.2MCUSim-0.2

Milestone renamed

Note: See TracTickets for help on using tickets.